FIG. 1 is a block diagram illustrating a typical clock signal output apparatus.
A known clock signal output apparatus 10 includes a digital phase detector (DPD) 11, an internal high-precision oscillator 12, an analog PLL circuit 13 (APLL), a digital loop filter (DLF) 14, a digital-to-analog (D/A) converter 15, a voltage-controlled oscillator (VCO) 16, and a frequency divider 17.
The digital phase detector 11 counts the phase difference between a reference clock signal REF_CLK and a feedback clock signal FB_CLK and outputs a digital phase difference signal representing the phase difference.
The digital phase detector 11 includes an analog phase detector that outputs the phase difference between a reference clock signal REF_CLK and a feedback clock signal FB_CLK, and a digital counter that counts the phase difference. The phase difference output from the analog phase detector is counted by using the digital counter, and the counted phase difference is output as a digital phase difference signal. For counting performed by the digital counter, a phase difference count clock signal DPD_CLK supplied from the internal high-precision oscillator 12 via the analog PLL circuit 13 is used.
The internal high-precision oscillator 12 is an oscillator for generating a phase difference count clock signal DPD_CLK used in counting the phase difference by using the digital counter in the digital phase detector 11. The phase difference count clock signal DPD_CLK is input to the digital phase detector 11 via the analog PLL circuit 13.
The digital loop filter 14 includes a processor such as a digital signal processor (DSP). The digital loop filter 14 averages error signals generated on the basis of a phase difference detected by the digital phase detector 11 (digital phase difference signal) and outputs the average.
The D/A converter 15 is a converter that converts the error signal output from the digital loop filter 14 into an analog signal and outputs the analog signal. The error signal output from the digital loop filter 14 is converted into an analog voltage value for controlling the oscillation frequency of the voltage-controlled oscillator 16.
The voltage-controlled oscillator 16 is an oscillator used as a slave oscillator. For example, an oscillator including an element such as a varicap diode that has a variable capacitance can be used as the voltage-controlled oscillator 16. By applying the analog voltage value output from the D/A converter 15 across the P-N junction of the varicap diode, a clock signal CLK with an oscillation frequency in accordance with the error signal output from the digital loop filter 14 is output. The clock signal CLK output from the voltage-controlled oscillator 16 is supplied to an electronic device such as a communication device or a video device and is used as a reference clock signal or the like.
The frequency divider 17 receives, as an input, the clock signal CLK output from the voltage-controlled oscillator 16 and outputs a feedback clock signal FB_CLK whose frequency is a fraction of the frequency of the clock signal CLK to the digital phase detector 11.
In the known clock signal output apparatus 10 as above, the clock signal CLK output from the voltage-controlled oscillator 16 is input to the frequency divider 17 and is output as a feedback clock signal FB_CLK whose frequency is a fraction of the frequency of the clock signal CLK to the digital phase detector 11. Using the phase difference count clock signal DPD_CLK supplied from the internal high-precision oscillator 12 via the analog PLL circuit 13, the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is counted. The counted phase difference is output as a digital phase difference signal.
The digital loop filter 14 averages error signals generated on the basis of the digital phase difference signal output from the digital phase detector 11, and inputs an error signal serving as the average to the D/A converter 15.
The D/A converter 15 converts the error signal output from the digital loop filter 14 into an analog signal (analog voltage value) and supplies the analog voltage value to the voltage-controlled oscillator 16.
The analog voltage value supplied from the D/A converter 15 to the voltage-controlled oscillator 16 is applied across the P-N junction of the varicap diode, thereby changing the capacitance of the varicap diode. Thus, a clock signal CLK with an oscillation frequency in accordance with the error signal output from the digital loop filter 14 is output from the voltage-controlled oscillator 16.
Accordingly, control is performed so that the frequency of the clock signal CLK output from the voltage-controlled oscillator 16, which is a slave oscillator, becomes synchronized with the reference clock signal REF_CLK.
In the known clock signal output apparatus 10, various improvements for highly accurately controlling the frequency of the clock signal CLK have been made (for example, see Japanese Laid-open Patent Publication Nos. 09-238070 and 2000-286697).
FIG. 2 is a block diagram illustrating a typical analog-digital convert apparatus including an analog-digital converter and the digital output apparatus 10, the analog-digital converter converting an analog video signal into a digital video signal by using the clock signal output from the digital output apparatus 10.
An analog-digital converter (hereinafter will be referred to as an “A/D converter”) 20 uses a clock signal supplied from the known clock signal output apparatus 10 as a sampling clock signal used in digitally sampling an analog video signal. Therefore, a clock signal output from the known clock signal output apparatus 10 needs to be synchronized with an analog video signal input to the A/D converter 20.
Here, three types of synchronizing signals are used for a video signal. The three types are a horizontal synchronizing signal (HSYNC) for achieving horizontal synchronization, a vertical synchronizing signal (VSYNC) for achieving vertical synchronization, and a composite synchronizing signal (CSYNC). Among the three types, the horizontal synchronizing signal (HSYNC) is synchronized with an analog video signal input to the A/D converter 20.
The composite synchronizing signal (CSYNC) is a signal combining the vertical synchronizing signal (VSYNC) and the horizontal synchronizing signal (HSYNC) and is given by an AND of the vertical synchronizing signal (VSYNC) and the horizontal synchronizing signal (HSYNC).
In the known clock signal output apparatus 10 illustrated in FIG. 2, the composite synchronizing signal (CSYNC) is used as the reference clock signal REF_CLK.
Therefore, in the known clock signal output apparatus 10, a clock signal generated so as to be synchronized with the composite synchronizing signal (CSYNC) is input as a sampling clock signal to the A/D converter 20.
That is, a sampling clock signal generated on the basis of the composite synchronizing signal (CSYNC) needs to be synchronized with an analog video signal input to the A/D converter 20.
FIG. 3 is a timing chart illustrating an example of the horizontal synchronizing signal (HSYNC), the vertical synchronizing signal (VSYNC), and the composite synchronizing signal (CSYNC). As illustrated in FIG. 3, the horizontal synchronizing signal (HSYNC) has a pulse for each line, and the vertical synchronizing signal (VSYNC) has a pulse for each frame.
Since the composite synchronizing signal (CSYNC) is given by an AND of the horizontal synchronizing signal (HSYNC) and the vertical synchronizing signal (VSYNC), as in a section A, each frame includes a section A in which the composite synchronizing signal (CSYNC) is maintained at a low level (L level).